In recent years, semiconductor wafers such as silicon wafers have a problem of the magnitude of surface waviness components, which are called “nanotopography”. Nanotopography is a kind of surface shapes of semiconductor wafers and shows a wavelength component with λ of 0.2 to 2.0 mm, which is shorter than the wavelength of “Sori” or “Warp” and longer than the wavelength of “surface roughness”. The nanotopography has an extremely shallow waviness with a peak-to-valley (PV) value of 0.1 μm to 0.2 μm.
Nanotopography of mirror-polished semiconductor wafers obtained through a double-side polishing step, which is a final step in processing of semiconductor wafers, is usually measured by an optical interference measurement apparatus. However, this reflection interference measurement apparatus fails to measure nanotopography of semiconductor wafers having a non-mirror main surface, which are on an intermediate step, such as a slicing step or a double-disc grinding step, and not subjected to mirror polishing.
Patent Document 1 discloses a method for calculating nanotopography of non-mirror semiconductor wafers by subjecting a warpage shape determined with a capacitive shape measurement apparatus to an arithmetic bandpass filter processing. This method enables simple measurement of nanotopography. A PV value of a cross-sectional shape (a difference between maximum displacement and minimum displacement) is used as a quantitative value of the simplified nanotopography. Hereinafter, this value is referred to as “pseudo-nanotopography”.
In addition, silicon wafers are also earnestly required to improve their flatness, as well as nanotopography. While conventional silicon wafers are required to have a flatness (SFQR) of 0.13 μm or less, recent silicon wafers are required to have a flatness (SFQR) of 0.07 μm or less, more strictly 0.04 μm or less.
Nanotopography is formed during processing of wafers (during the period from a slicing step to a polishing step). The nanotopography formed in a slicing step remains until a final step unless reduced in a double-disc grinding step. It is said that the nanotopography affects yields of shallow trench isolation (STI) processes in device production.
Patent Document 2 discloses a method for reducing nanotopography formed in a grinding step. This method includes adjusting the flow rate of a static pressure water to be supplied to a static pressure pad for supporting a wafer without contact in a double-disc grinding apparatus to reduce nanotopography formed in a double-disc grinding step.